Funvizeo https://www.funvizeo.com/ Fri, 27 Dec 2024 22:12:25 -0800 Joomla! - Open Source Content Management en-gb [email protected] (Funvizeo) SystemVerilog `define Macro https://www.funvizeo.com/systemverilog/systemverilog-define-macro https://www.funvizeo.com/systemverilog/systemverilog-define-macro

In Verilog, a `define macro is a powerful feature that allows for global text substitution in your code. It is a compiler directive that enables developers to define reusable code snippets or constants that can be easily referenced throughout the design.

[pre verilog] `define WIDTH 16 // Define macro WIDTH, substitute 16 `define EN_ADDR // Define macro EN_ADDR, substitute nothing wire [`WIDTH-1:0] addr; // Declares a 16-bit wire `ifdef EN_ADDR // Instantiate an adder if EN_ADDR macro is defined genvar i; generate // Code to instantiate an adder endgenerate `endif [/pre]

Read more on Verilog `define Macros !

 ]]> [email protected] (Admin) SystemVerilog Tue, 12 Nov 2024 20:16:26 -0800 Verilog $random https://www.funvizeo.com/verilog/verilog-random https://www.funvizeo.com/verilog/verilog-random
  1. Syntax

The system function $random provides a way to generate random numbers in Verilog. Each time it is called, the function returns a new 32-bit random number, which is a signed integer that can be either positive or negative.

Syntax

[pre verilog] $random([seed]); [/pre]

The seed argument controls the output of the $random function, ensuring that different seeds produce distinct random streams. This seed argument can be a reg, an integer, or a time variable. It is important to assign a value to this variable before calling $random.

]]> [email protected] (Admin) Verilog Fri, 08 Nov 2024 21:53:44 -0800 Verilog VCD Dump https://www.funvizeo.com/verilog/verilog-dump-vcd https://www.funvizeo.com/verilog/verilog-dump-vcd

A VCD file is an ASCII file that includes header information, definitions of variables, and the value changes for all variables specified in the task calls. Various system tasks can be incorporated into the source description to create and manage the VCD file.

Read more on Value Change Dump (VCD) !

Simulation variables can be dumped into a VCD file using the following tasks:

]]> [email protected] (Admin) Verilog Fri, 08 Nov 2024 08:12:11 -0800 Verilog VCD https://www.funvizeo.com/verilog/verilog-vcd https://www.funvizeo.com/verilog/verilog-vcd

VCD files, or Value Change Dump files, are a standardized ASCII format used to store simulation data from Verilog and other hardware description languages. They are primarily utilized for recording and analyzing the changes in values of variables during a simulation.

VCD files are generated by simulation tools to capture the state changes of signals over time. This data can be visualized using waveform viewers, allowing designers to analyze the behavior of their digital designs.

]]> [email protected] (Admin) Verilog Thu, 07 Nov 2024 08:38:32 -0800 Verilog Namespace https://www.funvizeo.com/verilog/verilog-namespace https://www.funvizeo.com/verilog/verilog-namespace
  1. Global Namespace

In Verilog, namespaces are a way to organize and manage identifiers (such as variables, types, tasks, and functions) to avoid naming conflicts and improve code modularity. There are multiple namespaces; two are classified as global, while the others are local. The global namespaces consist of definitions and text macros.

Global Namespace

The definitions namespace consolidates all module and primitive definitions. Once a name is assigned to a module or primitive, it cannot be reused to declare another module or primitive.

[pre verilog] module A; // Statements endmodule // cannot use 'module A' because it is already declared in global namespace module B; // Statements endmodule [/pre] ]]> [email protected] (Admin) Verilog Wed, 06 Nov 2024 18:07:59 -0800 Verilog $stop $finish https://www.funvizeo.com/verilog/verilog-stop-finish https://www.funvizeo.com/verilog/verilog-stop-finish
  1. $stop

In Verilog, the $stop and $finish system tasks are both used to end the simulation, but they serve different purposes.

These are called simulation control system tasks and is typically used in a testbench to end advancement of time, especially if there is an infinite loop by a forever loop or an always block with no sensitivity list. Note that initial blocks exit automatically after executing all statements within it.

$stop

[pre verilog] $stop([N]); // where N is // 0 : Prints nothing // 1 : Prints simulation time and location // 2 : Prints simulation time, location, and statistics about the memory // and central processing unit (CPU) time used in simulation [/pre]

The $stop task is used to pause the simulation at a specific point. When invoked, it effectively acts like a breakpoint, allowing the user to inspect the current state of the simulation without terminating it. You can resume the simulation manually after examining the state.

]]> [email protected] (Admin) Verilog Tue, 05 Nov 2024 22:12:13 -0800 Verilog Specify Block https://www.funvizeo.com/verilog/verilog-specify-block https://www.funvizeo.com/verilog/verilog-specify-block
  1. What is a specify block ?

What is a specify block ?

Two types of HDL constructs are commonly employed to define delays in structural models, such as ASIC cells.

  • Distributed Delays: These delays specify the time it takes for events to propagate through gates and interconnecting nets within a module.

  • Module Path Delays: These delays describe the time required for an event at a source (such as an input or inout port) to propagate to a destination (like an output or inout port).
]]> [email protected] (Admin) Verilog Tue, 05 Nov 2024 18:11:17 -0800 Verilog FSM https://www.funvizeo.com/verilog/verilog-fsm https://www.funvizeo.com/verilog/verilog-fsm
  1. Types of FSMs

Types of FSMs

There are two classifications of state machines based on the nature of their output generation:

  • Moore: In this type, the outputs depend solely on the current state.
  • Mealy: In contrast, this type generates one or more outputs that are influenced by both the current state and one or more inputs.

Beyond categorizing state machines by their output generation methods, they are also frequently classified based on the state encoding used. State encoding refers to how the different states of a state machine are represented in binary form.

  • Binary: Each state is represented using standard binary numbers (e.g., 00, 01, 10, 11).
  • One-Hot: Each state is represented by a binary vector where only one bit is '1' (hot) and all others are '0'.
]]> [email protected] (Admin) Verilog Sun, 03 Nov 2024 09:36:26 -0800 Verilog sdf_annotate https://www.funvizeo.com/verilog/verilog-sdf-annotate https://www.funvizeo.com/verilog/verilog-sdf-annotate
  1. What is SDF Backannotation ?

What is SDF Backannotation ?

SDF backannotation refers to the process of incorporating timing information like path delays, specparam values, timing constraint values and interconnect delays from a Standard Delay Format (SDF) file into a netlist during simulation. This technique is crucial for ensuring that the timing characteristics of a digital design are accurately represented, particularly after synthesis and layout.

]]> [email protected] (Admin) Verilog Wed, 30 Oct 2024 07:53:50 -0700 Gate Level Simulations https://www.funvizeo.com/verification/verification-gate-level-simulation https://www.funvizeo.com/verification/verification-gate-level-simulation What is Gate Level Simulation (GLS) ?

Gate Level Simulation (GLS) is a crucial step in the digital design verification process, occurring after the synthesis of the Register Transfer Level (RTL) code. It involves simulating the behavior of a circuit at the gate level, using a netlist that represents the circuit in terms of logic gates and their interconnections.

]]> [email protected] (Admin) Verification Sun, 27 Oct 2024 17:32:42 -0700