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Learn Verilog !
1. Introduction
  What is Verilog?
  Introduction to Verilog
  ASIC Design Flow
  Design Abstraction Layers

Examples
  Verilog Examples

2. Data Types
  Verilog Syntax
  Verilog Data types
  Verilog Scalar/Vector
  Verilog Arrays
  Verilog Net Types
  Verilog Strength

3. Building Blocks
  Verilog Module
  Verilog Port
  Verilog Module Instantiations
  Verilog assign statements
  Verilog assign examples
  Verilog Operators
  Verilog Concatenation
  Verilog always block
  Combo Logic with always
  Sequential Logic with always
  Verilog initial block
  Verilog generate
  Verilog Quick Review

4. Behavioral Modeling
  Verilog Block Statements
  Verilog Assignment Types
  Verilog Blocking/Non-blocking
  Verilog Control Flow
  Verilog for Loop
  Verilog case Statement
  Verilog Conditional Statements
  Verilog if-else-if
  Verilog Functions
  Verilog Tasks
  Verilog Parameters
  Verilog Delay Control
  Verilog Inter/Intra Delay
  Verilog Hierarchical Reference

5. Gate/Switch Modeling
  Gate Level Modeling
  Gate Level Examples
  Gate Delays
  Switch Level Modeling
  User-Defined Primitives

6. RTL Simulation
  Verilog Simulation Basics
  Verilog Testbench
  Verilog Timescale
  Verilog Scheduling Regions
  Verilog Clock Generator

7. Gate Level Simulation
  Gate Level Simulations
  Verilog Timing Checks
  Verilog Specify Block
  Standard Delay Format (SDF)
  Verilog sdf_annotate

8. Synthesis
  Verilog Synthesis
  Verilog Coding Style Effect

9. Verilog Macros
  Verilog Compiler Directives
  Verilog Macros
  Verilog `ifdef `elsif

10. System Tasks and Functions
  Verilog $random
  Verilog $stop and $finish
  Verilog Display tasks
  Verilog Math Functions
  Verilog Conversion Functions
  Verilog Timeformat
  Verilog Timescale Scope
  Verilog File Operations
  Verilog Command Line Input

11. Miscellaneous
  Verilog Namespace
  Value Change Dump (VCD)
  Verilog VCD Dump

Verilog Examples

Hello World!

Flip-Flops and Latches

  • JK Flip Flop
  • D Flip-Flop Async Reset
  • Verilog T Flip Flop
  • D Latch

Counters

  • 4-bit counter
  • Ripple Counter
  • Straight Ring Counter
  • Johnson Counter
  • Mod-N Counter
  • Gray Counter

Digital Elements

  • n-bit Shift Register
  • Binary to Gray Converter
  • Priority Encoder
  • 4x1 multiplexer
  • Full adder

Misc

  • Single Port RAM
  • Verilog Pattern Detector
  • Verilog Sequence Detector
  • Synchronous FIFO
  • Verilog Stack or LIFO
Interview Questions
  Verilog Interview Set 1
  Verilog Interview Set 2
  Verilog Interview Set 3
  Verilog Interview Set 4
  Verilog Interview Set 5
  Verilog Interview Set 6
  Verilog Interview Set 7
  Verilog Interview Set 8
  Verilog Interview Set 9
  Verilog Interview Set 10
  Verilog Interview Set 11
  Verilog Interview Set 12
  Verilog Interview Set 13
  Verilog Interview Set 14
  Verilog Interview Set 15


Related Topics
  Digital Fundamentals
  Verilog Tutorial

  Verification
  SystemVerilog Tutorial
  UVM Tutorial
Latest in Verilog
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Latest in SystemVerilog
  • SystemVerilog Callback
  • SystemVerilog Interview Questions Set 10
  • SystemVerilog Interview Questions Set 9
  • SystemVerilog Interview Questions Set 8
  • SystemVerilog Interview Questions Set 7
Latest in UVM
  • UVM Callback
  • UVM Singleton Object
  • UVM Component [uvm_component]
  • UVM Object [uvm_object]
  • UVM Root [uvm_root]
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