Verilog $stop $finish

In Verilog, the $stop and $finish system tasks are both used to end the simulation, but they serve different purposes.

These are called simulation control system tasks and is typically used in a testbench to end advancement of time, especially if there is an infinite loop by a forever loop or an always block with no sensitivity list. Note that initial blocks exit automatically after executing all statements within it.

$stop

  $stop([N]);

  // where N is
  // 0   :   Prints nothing
  // 1   :   Prints simulation time and location
  // 2   :   Prints simulation time, location, and statistics about the memory
  //         and central processing unit (CPU) time used in simulation

The $stop task is used to pause the simulation at a specific point. When invoked, it effectively acts like a breakpoint, allowing the user to inspect the current state of the simulation without terminating it. You can resume the simulation manually after examining the state.

To resume the simulation, you will use specific commands provided by your simulation tool. The exact command may vary depending on the simulator you are using (e.g., ModelSim, VCS, or other tools).

module tb;

reg [3:0] counter;

initial begin
    counter = 0;
    #10 counter = counter + 1; // Increment after 10 time units
    $display("Counter value before stop: %b", counter);
    
    $stop; // Simulation pauses here

    // This line will not execute until the simulation is resumed
    #10 counter = counter + 1;
    $display("Counter value after stop: %b", counter);
end
endmodule

In this example:

• The simulation increments counter and displays its value.
• The $stop task is called, pausing execution.
• After resuming, it increments counter again and displays the new value.

$finish

  $finish([N]);

  // where N is
  // 0   :   Prints nothing
  // 1   :   Prints simulation time and location
  // 2   :   Prints simulation time, location, and statistics about the memory
  //         and central processing unit (CPU) time used in simulation

The $finish task is used to terminate the simulation entirely. When this task is encountered, it stops all simulation processes and returns control to the operating system. This task is typically used when the simulation completes successfully or when an unrecoverable error occurs.

module tb;

initial begin
    
    // Some simulation code...
    #10 $display("Waited to 10 units");
    
    // Terminate simulation and print a diagnostic message
    $finish(1); 

    // This delay will never be executed in simulation because it will be 
    // terminated by the line before
    #100;
end

endmodule

In this example:

• The $finish task is called, which ends the simulation immediately.
• Any code following $finish will not execute.

Difference between $stop and $finish

These distinctions make $stop useful for debugging scenarios while $finish is appropriate for concluding a testbench or simulation run.

By understanding how to utilize $stop effectively and knowing the commands specific to your simulator, you can enhance your debugging and simulation control capabilities significantly.