Verilog Specify Block

What is a specify block ?

Two types of HDL constructs are commonly employed to define delays in structural models, such as ASIC cells.

• Distributed Delays: These delays specify the time it takes for events to propagate through gates and interconnecting nets within a module.


• Module Path Delays: These delays describe the time required for an event at a source (such as an input or inout port) to propagate to a destination (like an output or inout port).

The specify block in Verilog is a specialized construct used to define timing characteristics and delays for signals within a module. It allows designers to specify delays across a module and perform timing checks, such as setup and hold times.

Syntax

It begins with the specify keyword and ends with endspecify.

specify

// Checks and Statements

endspecify

Inside this block, you can include:

• specparam declarations to define delays and timing parameters.
• Path declarations to describe the timing paths between input and output signals, assigning delays to these paths.
• System timing checks to enforce timing constraints on signal transitions.

Specify Example

module example_module (
    input wire a,
    input wire b,
    output wire out
);

specify
    // Specparam declaration to define timing parameters
    specparam TRise = 5; // Rise time delay
    specparam TFall = 3; // Fall time delay

    // Path declarations to specify delays between signals
    (a => out) = TRise;   // Delay from input 'a' to output 'out'
    (b => out) = TFall;   // Delay from input 'b' to output 'out'

    // System timing check for setup time
    $setup(a, out, 10);   // Check setup time for signal 'a' relative to 'out'
endspecify

// Logic for the output
assign out = a & b; // Example combinational logic

endmodule

Module Paths

The paths defined within the specify block, known as module paths, connect a signal source to a signal destination.

The source can be either unidirectional (an input port) or bidirectional (an inout port), and is referred to as the module path source.

Likewise, the destination can also be unidirectional (an output port) or bidirectional (an inout port), and is termed the module path destination. This must have only a single driver within the module.

A module path may be described as a simple path, an edge-sensitive path, or a state-dependent path.

Simple Module Paths

The operator *> creates a full connection between the source and destination. In contrast, the operator => establishes a parallel connection between the source and destination.

specify
    // Full connection using the (*>) operator
    (c, a *> z) = 5;  // Delay of 5 time units for a simple path from 'a' to 'z' or 'c' to 'z'
    
    // Parallel connection using the (=>) operator
    (b => y) = 10;  // Delay of 10 time units from input 'b' to output 'y'
endspecify

Edge Sensitive Paths

When a module path is defined using an edge transition at the source, it is referred to as an edge-sensitive path. This construct is utilized to model the timing of input-to-output delays that occur exclusively when a specified edge (posedge or negedge) is detected on the source signal.

If the edge transition is not specified, the path shall be considered active on any transition at the input terminal.

specify
    // Edge-sensitive path declaration
    (posedge clk *> data_out) = 5;  // Delay of 5 time units for the rising edge of 'clk' affecting 'data_out'
endspecify

State Dependent Paths

A state-dependent path allows for the assignment of a delay to a module path, affecting the signal propagation delay through that path only when specified conditions are met.

specify
    // State-dependent path declaration
    if (a) (enable => data_out) = 10;  // Delay of 10 time units when 'a' is true
    if (reset ==0) (enable => data_out) = 5; // Delay of 5 time units when 'reset' is low
endspecify

ifnone Condition

The ifnone keyword is utilized to define a default state-dependent path delay when all other conditions for the path are false. The ifnone condition must specify the same module path source and destination as the other state-dependent module paths.

specify    
    // Default state-dependent path delay using ifnone
    ifnone (enable => data_out) = (15.0, 15.0);           // Default delay of 15 time units when no other conditions are met
endspecify