What is SDF Backannotation ?
SDF backannotation refers to the process of incorporating timing information like path delays, specparam values, timing constraint values and interconnect delays from a Standard Delay Format (SDF) file into a netlist during simulation. This technique is crucial for ensuring that the timing characteristics of a digital design are accurately represented, particularly after synthesis and layout.
During simulation, each cell in the netlist retrieves its corresponding delay values from the SDF file. These delays are then annotated to the relevant instances or paths in the netlist, effectively replacing or modifying the default timing values that were initially assigned during synthesis.
$sdf_annotate
The $sdf_annotate system task in Verilog is commonly used to implement backannotation. This command tells the simulator to read the specified SDF file and apply its timing information to the designated instance of the design.
initial begin
$sdf_annotate("/path/to/timing_data.sdf", top_level_instance);
end
SDF Annotator
An SDF annotator is any tool that can back-annotate SDF data to a Verilog simulator. It should issue a warning if it encounters data that it cannot annotate.
elab: *W, SBNFSDF: Attempt to annotate specify block data of instance tb.DUT.path_to_cell of module example, which has no specify block <path/to/timing_data.sdf>, line 56531>
An SDF file may include various constructs that are unrelated to specify path delays, specparam values, timing check constraints, or interconnect delays.
All constructs not relevant to Verilog timing should be ignored without warnings. If the SDF file lacks a value for a specific Verilog timing parameter, that parameter should remain unmodified during back-annotation, retaining its pre-backannotation value.
Annotating SDF timing data:
Compiled SDF file: /path/to/timing_data.sdf
Backannotation scope: tb.DUT.path_to_module_inst
// Other info
SDF statistics:
No of Pathdelays = 12412 ... Annotated = 100.0%
Total Annotated
Path Delays 12412 12412
$period 113 0
$width 1214 0
$setup 63234 62412
$hold 63234 62412
Always review the SDF annotator tool log to ensure simulations are conducted with a high percentage of annotations.
SDF Contents
SDF timing values are specified within a CELL declaration, which may include one or more sections: DELAY, TIMINGCHECK, and LABEL. The DELAY section provides propagation delay values for specify paths and interconnects, while the TIMINGCHECK section contains timing constraint values. The LABEL section assigns new values to specparams.
(CELL
(CELLTYPE "a01_ce12v124b")
(INSTANCE u0_path/u1_to/u2_reg)
(DELAY
(ABSOLUTE
(COND en_clk==1'b1 (IOPATH clk_i clk (0.0151::0.0168) (0.0221::0.235)))
...
)
(TIMINGCHECK
(WIDTH (COND some_signal==1'b1 (negedge clk)) (0.0211::0.0514)))
(SETUPHOLD (posedge en_clk) (COND some_signal==1'b1 (posedge clk)) (0.0241:0.255) (-0.0111::-0.102))
...
)
)
When annotating DELAY constructs that are not interconnect delays, the SDF annotator searches for specify paths with matching names and conditions. For TIMINGCHECK constructs, the SDF annotator looks for timing checks of the same type, also ensuring the names and conditions match.
Mapping of SDF Paths
Note that the CELL contains path to the exact instance in design hierarchy where it needs to be applied.
// SDF file:
(IOPATH clk_i clk (0.0151::0.0168) (0.0221::0.235)
// Verilog specify path:
(clk_i => clk) = 0;
In the above example, the source SDF signal clk_i matches the source Verilog signal and the destination SDF signal clk also matches the destination Verilog signal. So, the rise/fall times of 0.0151 and 0.0168 are annotated to the specify path.
A conditional IOPATH delay between two ports shall annotate only to Verilog specify paths between those same two ports with the same condition.
// SDF file:
(COND en_clk==1'b1 (IOPATH clk_i clk (0.0151::0.0168) (0.0221::0.235)))
// Verilog Specify Paths:
if (en_clk) (clk_i => clk) = 0;
SDF Annotation of specparams
The SDF LABEL construct is used to annotate specparam. When an expression contains one or more specparam, it is reevaluated upon annotation from an SDF file.
// SDF file:
(LABEL
(ABSOLUTE
(high_dc 30)
(low_dc 20))
// Verilog file:
module my_des(output reg signal);
specparam high_dc=0, low_dc=0;
specparam xyz=0;
always begin
#high_dc signal = 1;
#low_dc signal = 0;
end
specify
(B => Y) = 0.2 * xyz + 1.0;
endspecify
endmodule
