Funvizeo logo

Standard Delay Format (SDF)

  1. What is SDF ?
  2. What is it used for ?
  3. Structure of SDF
    1. Header Section
    2. Cell and Instance Definitions
    3. Path Delays
    4. Timing Checks
  4. Application of SDF
  5. How is SDF used in Gate Level Simulations ?

What is SDF ?

Standard Delay Format (SDF) is an IEEE standard (IEEE 1497) used extensively in electronic design automation (EDA) for representing timing information associated with digital circuits. It is in ASCII format and includes path and interconnect delays and timing constraint checks.

What is it used for ?

SDF serves as a bridge between dynamic and static timing analysis, allowing for accurate representation of delays within digital circuits. It is widely used in various stages of the design flow to ensure that timing requirements are met.

sdf example
  • Timing Representation: SDF provides a standardized way to describe delays associated with digital components, including gates, flip-flops, and interconnects. This is essential for ensuring that the design meets its timing requirements.

  • Interoperability: By using a common format, SDF facilitates communication between different EDA tools. This allows designers to use various tools for synthesis, simulation, and timing analysis without worrying about compatibility issues.

  • Back-Annotation: SDF is often used for back-annotation, where timing data calculated during the post-layout phase is added to the simulation environment. This helps ensure that simulations reflect the actual delays present in the physical implementation of the design.

  • Forward Annotation: In some cases, SDF can also be used for forward annotation, where timing information is provided to tools before synthesis to guide optimization processes.

Structure of SDF

An SDF file consists of several key sections:

Header Section

Contains general information about the SDF like version, design name, date, timescale, and PVT corners.


(SDFVERSION "3.10")
(DESIGN "PROTOTYPE")
(DATE "October 27, 2009 12:31")
(VENDOR "SOME_EDA")
(VOLTAGE 1.1:0.9:0.8)
(PROCESS "min:typ:max")
(TEMPERATURE -40:25:125)
(TIMESCALE 1ns)

Cell and Instance Definitions

Each cell or component in the design is defined here, along with its associated delays based on the specified timescale in the header section. It is essential to include at least one cell section, with no upper limit on the number of sections. The order of the cell sections is also significant.

For instance, if there are two cell sections defining the timing properties for the same part of the design, the information in one section can either override the existing data (ABSOLUTE) or be cumulative with it (INCREMENTAL).


(CELL (CELLTYPE "AND2")
      (INSTANCE "U1")
      (DELAY (ABSOLUTE
          (INTERCONNECT (0.1::0.2) (0.3::0.4))
          (CELL (0.5::0.6) (0.7::0.8)))))

In this example, CELLTYPE specifies the type of logic gate. INSTANCE indicates a specific instance of that gate in the design. DELAY describes various types of delays - INTERCONNECT delays represent delays caused by wiring between components and CELL delays represent intrinsic delays of the component itself.

Path Delays

Describes delays associated with specific paths through the circuit, which are critical for static timing analysis.


(PATH (A "U1/A") (B "U2/B") 
      (DELAY (ABSOLUTE (0.2::0.3))))

Timing Checks

Includes checks for setup time, hold time, recovery time, and removal time.


(CHECKS
    (SETUP "U1/A" "U2/B" 5)
    (HOLD "U1/A" "U2/B" 2)
)

Read more on Verilog Timing Checks !

Application of SDF

  • Static Timing Analysis: SDF files are integral to static timing analysis tools that verify whether a design meets its timing constraints without requiring dynamic simulation.

  • Post-Layout Verification: After layout synthesis, SDF files provide accurate delay information that reflects the actual physical characteristics of the circuit, allowing designers to validate performance against specifications.

  • Simulation: Timing data from SDF files can be used in simulations to ensure that signal timings are respected during operation, helping to identify potential timing violations before fabrication.

  • Design Optimization: By providing detailed delay information, SDF allows optimization tools to make informed decisions about how to rearrange or modify circuit elements to meet timing requirements.

How is SDF used in Gate Level Simulations ?

Standard Delay Format (SDF) is primarily used for back-annotating timing information to enhance the accuracy of timing simulations.

After synthesizing a design, it is essential to verify that it meets timing requirements under real-world conditions. SDF files provide the necessary timing data derived from the layout process, including propagation delays and interconnect delays.

SDF files are used for back-annotation in simulations. This means that after layout synthesis, the timing information contained in the SDF file is applied to the gate-level netlist to account for delays introduced during physical design.

Performing a final simulation with back-annotated timing information helps ensure that unexpected delays do not lead to timing violations in the design.