Async resets of some FFs are driven by other FFs, how does this affect testability ?

During scan testing, if the driving FF gets a pattern such that it resets the driven FF, it will lose its data. Hence the reset output from the first FF should be OR'd with a test mode enable signal before assigning to the second FF.

Read more: Verilog Interview Questions Set 15

What happens to the bits of a reg which are declared, but not assigned or used?

Bits that are unused are optimized away during synthesis.

module design (...);

reg [3:0] tmp;

always @ (posedge clk) begin
	if (! resetn) begin
		tmp <= 0;
                
	// Since tmp[1] and tmp[2] are unused,
    // synthesized logic will contain only 2 flops
	end else begin
    	tmp[0] <= in;
		tmp[3] <= ~in;
	end
end

endmodule

Read more: Verilog Interview Questions Set 14

What are a few considerations while partitioning large designs?

• Size and complexity of the design: A large design will need to be partitioned into a number of smaller designs. This can affect how the design is divided into different sections and the size of each partition.
• Clock Domains: It is recommended to group logic belonging to same clock domain in a single block, and clock domain crossings done thorugh a synchronizer.
• Specific design requirements: Specific design requirements, such as timing or power constraints, will affect how the design is partitioned.
• Vendor's requirements: The vendor's requirements must also be considered as the partitioning of designs will be determined largely by their manufacturing capabilities.

Read more: Verilog Interview Questions Set 13

Explain the differences and advantages of casex and casez over the case statement?

casex has to be used when both X and Z needs to be treated as don't care for comparisons with the case item. casez on the other hand only treats Z as don't care.

casex (abc)
	3'bx00  : out = a & b; 		// same as 3'b000 and 3'b100
	3'b10x  : out = a | b; 		// same as 3'b100 and 3'b101
	default : out = ~(a & b); 	// for cases where bits in abc can be X or Z
endcase

Here are a couple of advantages:

• Synthesis optimization: casex and casez can be optimized more effectively by synthesis tools than the case statement. This is because casex and casez allow for more efficient encoding of the match conditions, reducing the number of gates required to implement the logic.
• Code readability: casex and casez can make Verilog code more readable and concise. This is because they allow for more complex matching logic to be expressed in a single statement, rather than requiring multiple if-else statements.

What are the differences between synchronous and asynchronous state machines?

Synchronous state machines have a clock input that triggers state transitions at specific times. When the clock signal rises, the state machine updates its output values and transitions to the next state based on its current state and input values.

Asynchronous state machines do not require a clock signal as they are triggered by input signals that are not synchronized in time. Each input signal can trigger a state transition at any time, independent of any clock signal. Asynchronous state machines can be more complex to design and test due to the possibility of race conditions and glitches, but they can be more efficient and consume less power compared to synchronous state machines.

Illustrate the differences between Mealy and Moore state machines.

Mealy State Machine:

• Outputs are a function of both current state and inputs.
• Output may not be stable for one clock cycle as it is a function of input and current state.
• Output is prone to glitches.
• State transitions are based on both the current state and input signals.
• If inputs are not registered, combinational paths could potentially be larger than Moore machine, less operating frequency.

Moore State Machine:

• Output is based solely on the current state
• Output is stable for one clock cycle.
• Output is not prone to glitches.
• State transitions are based solely on the current state.
• Combinational paths are typically shorter with no involvement of inputs.

Illustrate the differences between binary encoding and one-hot encoding mechanisms state machines.

In binary encoding, each state is represented by a unique binary code, where each bit of the code represents a possible state in the state machine. For example, if a state machine has four possible states, it can be represented using two bits (00, 01, 10, and 11).

• Binary encoding uses fewer flip-flops compared to one-hot encoding, which makes it more efficient in terms of hardware utilization.
• Timing is not as good as one-hot encoding due to more combinatorial paths
• Requires more effort for maintenance and debug
• Usually preferred in ASICs unless output path timing is critical

In one-hot encoding, each state is represented by a unique bit, with only one bit set to 1 and all other bits set to 0. For example, in a state machine with four possible states, each state is represented by a unique combination of four bits, with only one bit set to 1.

• The state transitions are clearly defined, which makes it easier to detect errors and glitches in the state machine
• One-hot encoding has a faster response time compared to binary encoding since only one bit changes state at a time and there's only clk->q delay
• It is easier to design and debug state machines using one-hot encoding
• Useful in register rich applications like FPGAs

Explain a reversed case statement, and how it can be useful to infer a one-hot state machine?

A case expression can be a constant used to match against a variable also.

// 4-bit variable to store 4 states in one-hot encoding
reg [3:0] cur_state, next_state;

case (1'b1)
	cur_state[0] : // Assign next state 
	cur_state[1] : // Assign next state
	cur_state[2] : // Assign next state
	cur_state[3] : // Assign next state
endcase

Illustrate how a multi-dimensional array is implemented.

Synchronous static memories that can be used like a register file can be defined as a multi-dimensional array which then gets synthesized into FFs. For the example below, each row of memory requires 8 FF, and with a depth of 16, the total FFs required will be 128.

parameter DEPTH = 16;
parameter WIDTH = 8;

reg [WIDTH-1:0] mem [DEPTH-1:0];

always @ (posedge clk) begin
	if (wr)
		mem[addr] <= i_data;
	else
		o_data <= mem[addr];                           
end	

Using a hardmacro of memory from a semiconductor vendor with better area and power would be better than synthesizing it using discrete logic.

What are the considerations in instantiating technology specific memories?

When instantiating technology-specific memories, there are several key considerations to keep in mind to ensure optimal performance and efficiency:

• Area: A high density memory would be required to reduce area footprint of the design on the die, typically used by chips with large memory blocks.
• Frequency: Special high-speed memory cells that operate at high frequencies may be required if speed is the main concern, but it may have larger area.
• Power requirements: The power consumption of the memory should be considered, especially in low-power applications. Memories such as DRAM and SRAM typically require low power, while NAND flash memory requires higher power.
• Memory type: Depending on the application, the appropriate memory technology should be selected, such as SRAM, DRAM, or flash memory, each with their own advantages and disadvantages.
• Memory access speed: The memory access speed should be chosen based on the performance requirements of the system. DDR memory provides high-speed access, whereas NOR flash memory provides fast read access.
• Pinout and package options: The pinout and package options should be selected based on the available space and required signal requirements of the system.
• Single vs Multi Port: Depends on overall design architecture required to support a targeted performance of the system. Multiple ports allow write and read transactions to happen concurrently thereby boosting its performance.
• Voltage requirements: The voltage requirements of the memory should also be taken into account to ensure compatibility with the power supply and other components in the system.
• Cost: The cost of the memory should be evaluated against the benefits provided to ensure that it is a cost-effective solution.

What are the factors that dictate the choice between synchronous and asynchronous memories?

• Performance: Synchronous memories are generally faster than asynchronous memories and synchronize data transfer with a clock signal. For applications that require high-speed data transfer, synchronous memory is the better choice.
• Latency: Asynchronous memories typically have higher read and write latencies whereas synchronous memories have predictable latencies and faster cycle times. Asynchronous memories may be acceptable for applications that can tolerate higher latencies.
• Power Consumption: Asynchronous memories typically consume less power compared to synchronous memories since there's no internal clock signal making them desirable for power-sensitive applications.
• Timing: Synchronous memories have better static timing because data output is registered with a FF, whereas asynchronous memories have combinatorial paths that may become critical element in the timing path.
• Area: Synchronous memories require more area compared to asynchronous memories.
• Noise immunity: Synchronous memory has better noise immunity compared to asynchronous memory. The use of the clock signal makes it less vulnerable to electrical noise and other forms of interference.
• Cost: Asynchronous memories are less complex and easier to manufacture, making them more cost-effective compared to synchronous memories.

What are some reusable coding practices for RTL Design?

• Better timing closure can be achieved if all outputs of critical design blocks are registered.
• Avoid snake paths which make debugging tedious and synthesis difficult.
• Avoid instantiation of technology specific gates.
• Use parameters and macros instead of hard-coded values in design RTL.
• Breaking down functionality into smaller submodules can help to minimize the complexity of your code, which makes it more reusable.
• Use generic RTL code is general-purpose code that can be reused in many different applications.
• Develop your coding style to facilitate readability and maintenance. Consistent coding practices, such as standard naming conventions and formatting, can make your code more understandable and reusable.
• Intellectual property (IP) modules are proven, tested designs that have been created for reuse. Reusing IP modules can minimize the development time, cost, and risk associated with designing from scratch.
• Utilizing a standardized library with commonly used functions makes it easier to design and maintain RTL code across multiple projects.

What are snake paths, and why should they be avoided?

It is a path that goes through different levels of hierarchies and return to the same level where it started from. These should be avoided because it will have a long timing path and may turn out to be a critical path in chip top, and synthesis tools will have harder time to constrain paths leading to larger runtimes.

To avoid this:

• Register the outputs of modules with different functional objectives
• Partition the design functionality, and aim for short and direct routes between components.

What are the considerations to be taken choosing between flop-flops vs. latches in a design?

1. Functional requirements: The first consideration is the functional requirements of the system. Different types of flip-flops and latches have their specific functions and capabilities, and it is necessary to choose the appropriate type based on the system's requirements.
2. Timing requirements: Flip-flops have a fixed clock edge at which they latch the data, while latches hold the data as long as the enable signal is active. Latches facilitate time borrowing or cycle stealing, and helps increase pipeline depth with lesser area.
3. Power consumption: Flip-flops tend to consume more power than latches, as they operate continuously with a clock signal. If power consumption is a concern, latches may be preferred.

Read more: Verilog Interview Questions Set 11