What is the difference between logic and bit in SystemVerilog?
In SystemVerilog, a bit is a single binary digit that can have a value of 0 or 1, while logic is a data type used for representing a single wire or net that can have multiple states such as 0, 1, Z (high-impedance), X (unknown), or L (weakly driven low) and H (weakly driven high).
Read more on SystemVerilog Data Types.
Write pseudo code for implementing an AHB-Lite driver.
The main point in writing an AHB driver is to realize that its a pipelined protocol and hence address phase of the next transaction should be active when the data phase of current transaction is on going. This is done by starting the same task twice in a fork join.
How can we access a DUT signal in a component or sequence ?
Interface signals can be accessed via a virtual interface handle that points to the actual physical interface. Signals within the DUT can be accessed directly by providing a hierarchical RTL path to uvm_hdl_* functions such as.
uvm_hdl_force("top.eatable.fruits.apple.slice", 2);
uvm_hdl_deposit("top.eatable.fruits.apple.slice", 3);
uvm_hdl_read("top.eatable.fruits.apple.slice", rdata);
What are the different phases in UVM ?
The main phases in UVM are :
- build_phase
- connect_phase
- end_of_elaboration_phase
- start_of_simulation_phase
- run_phase
- extract_phase
- check_phase
- report_phase
- final_phase
Read more in UVM Phases.
What is a UVM RAL model ? Why is it required ?
RAL is short for Register Abstraction Layer. It is a set of base classes that can be used to create register models to mimic the register contents in a design. It is much easier to write and read from the design using a register model than sending a bus transaction for every read and write. Also the register model stores the current state of the design in a local copy called as a mirrored value. Read more in Register Layer.
