Is it possible to override existing constraints?

Yes, it's possible to override existing constraints in SystemVerilog using inline constraints or inheritance.

class ABC;
	rand bit [3:0] data;

	constraint c_data { data inside {[5:10]}; }
endclass

module tb;
	initial begin
		ABC abc = new;

		// Use inline constraint to override with new value
		// Note that this should not contradict the hard constraints in ABC
		abc.randomize() with { data == 8; };
	end
endmodule

Read more: SystemVerilog Interview Questions Set 4

What is virtual function?

In SystemVerilog, a virtual function is a type of function that allows a base class to define a function signature which can be overwritten in a derived class. This means that a virtual function can be customized by a subclass to perform a different function than the base class.

Virtual functions are an important aspect of object-oriented programming (OOP) and are used heavily in verification methodologies such as the Universal Verification Methodology (UVM). In UVM, virtual functions are used to customize the behavior of verification components and facilitate the reuse of code across different testbenches.

Read more: SystemVerilog Interview Questions Set 3

What is the difference between a deep copy and a shallow copy ?

A deep copy is one where nested class object contents are also entirely copied over into the new class object. A shallow copy is one where nested class objects are not copied but instead handles are simply assigned. So, if the original class object changes its contents, then the copied class also see the same contents.

Read more on SystemVerilog Copying Objects.

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How will you test the functionality of interrupts using functional coverage?

Testing the functionality of interrupts using functional coverage involves the following steps:

1. Define functional coverage goals: First, you need to define your functional coverage goals. These goals should be specific to the interrupts you want to test. For example, you might define goals for interrupt latency, interrupt frequency, or interrupt priority handling.
2. Create a testbench for interrupts: Next, you need to create a testbench that generates interrupts with different characteristics. This testbench should also monitor the behavior of the design under test (DUT) in response to the interrupts.
3. Implement functional coverage: You can then implement functional coverage in your testbench to track how often each of the defined functional goals is achieved. You can use standard SystemVerilog constructs like covergroups, coverpoints, and bins to define and track the functional coverage.
4. Analyze the functional coverage results: Finally, you can analyze the functional coverage results to determine how well your testbench tests the desired interrupt functionality. Based on the results, you can make adjustments to your testbench to improve the tests.

Read more: SystemVerilog Interview Questions Set 1

Net Types

In Verilog, net types are used to model physical connections between components in digital circuits. They do not store values, its value is determined by the values of its drivers and the default value of a net is typically 'z' (high impedance) when left unconnected.

Read more: Verilog Net Types