In Verilog, the $stop and $finish system tasks are both used to end the simulation, but they serve different purposes.
These are called simulation control system tasks and is typically used in a testbench to end advancement of time, especially if there is an infinite loop by a forever loop or an always block with no sensitivity list. Note that initial blocks exit automatically after executing all statements within it.
$stop
$stop([N]);
// where N is
// 0 : Prints nothing
// 1 : Prints simulation time and location
// 2 : Prints simulation time, location, and statistics about the memory
// and central processing unit (CPU) time used in simulation
The $stop task is used to pause the simulation at a specific point. When invoked, it effectively acts like a breakpoint, allowing the user to inspect the current state of the simulation without terminating it. You can resume the simulation manually after examining the state.
What is a specify block ?
Two types of HDL constructs are commonly employed to define delays in structural models, such as ASIC cells.
- Distributed Delays: These delays specify the time it takes for events to propagate through gates and interconnecting nets within a module.
- Module Path Delays: These delays describe the time required for an event at a source (such as an input or inout port) to propagate to a destination (like an output or inout port).
Types of FSMs
There are two classifications of state machines based on the nature of their output generation:
- Moore: In this type, the outputs depend solely on the current state.
- Mealy: In contrast, this type generates one or more outputs that are influenced by both the current state and one or more inputs.
Beyond categorizing state machines by their output generation methods, they are also frequently classified based on the state encoding used. State encoding refers to how the different states of a state machine are represented in binary form.
- Binary: Each state is represented using standard binary numbers (e.g., 00, 01, 10, 11).
- One-Hot: Each state is represented by a binary vector where only one bit is '1' (hot) and all others are '0'.
What is SDF Backannotation ?
SDF backannotation refers to the process of incorporating timing information like path delays, specparam values, timing constraint values and interconnect delays from a Standard Delay Format (SDF) file into a netlist during simulation. This technique is crucial for ensuring that the timing characteristics of a digital design are accurately represented, particularly after synthesis and layout.
What is Gate Level Simulation (GLS) ?
Gate Level Simulation (GLS) is a crucial step in the digital design verification process, occurring after the synthesis of the Register Transfer Level (RTL) code. It involves simulating the behavior of a circuit at the gate level, using a netlist that represents the circuit in terms of logic gates and their interconnections.
